Design
Usually an electronics engineer designs the circuit, and a layout specialist designs the PCB. The designer must obey numerous PCB layout guidelines to design a PCB that functions correctly, yet is inexpensive to manufacture. The standards organization JEDEC publishes design rules intended to ensure manufacturability of PCBs.
Electronic Design Automation (EDA)
PCB designers often use electronic design automation to produce a layout. The EDA program stores design information, facilitates editing the design, and can also automate repetitive design tasks.
The first stage is converting the circuit schematic into a net list. The net list is conceptually a list of component pins and the circuit nodes, or nets, that each pin connects to. Often the schematic capture EDA program, operated by a circuit design engineer, is responsible for netlist generation, and the netlist is imported into the PCB layout program.
The next step is to decide the position of each device. The easy way to do this is to specify a grid of lettered rows and numbered columns where the devices should go. The computer then assigns pin 1 of each device in the bill of materials to a grid location. Typically, the operator may assist the automated placement routine by specifying rooms, or specific regions of the board, where certain groups of components should be placed. For example, the parts associated with a power supply subcircuit might be assigned to a region near the power input connector. In other cases devices may be manually placed, either to optimize the electrical performance of the circuit, or to place components such as knobs, switches, and connectors as required by the mechanical design of the system.
The computer then explodes the device list into a complete pin list for the board by using templates from a library of footprints associated with each type of device. Each footprint is a map of a device's pins, usually with a recommended pad and drill hole layout for each device. The library allows the footprint to be drawn only once, and then shared by all devices of that type.
In some systems, high-current pads are identified in the device library, and the associated nets are flagged for attention by the pcb designer. High current runs require wider traces, and the designer or circuit design engineer usually decides the width. (If the currents are sufficiently high, that will also require that a heavier weight of copper foil on the laminate be specified.)
The computer program then merges the netlist (sorted by pin name) with the pin list (sorted by pin name), transferring the physical coordinates of the pin list to the netlist. The netlist is then resorted, by net name.
Some systems can optimize the design by swapping the positions of parts and logic gates to reduce the length of copper runs. Some systems also automatically discover power pins in the devices, and generate runs or vias to the nearest power plane or conductor.
The programs then try to route each net in the signal-pin list, finding some sequence of connections in the available layers. Often layers are assigned to power and ground, with one layer to vertical, and another to horizontal wires. The power layers shield the circuits from noise.
The routing problem is equivalent to the travelling salesman problem, and is therefore NP complete, and therefore not amenable to a perfect solution. One practical routing algorithm is to pick the pin farthest from the center of the board, then use a greedy algorithm to select the next-nearest pin with the same signal name.
After automated routing, usually there is a list of nets that must be manually routed.
Once routed, the system may have a series of strategy subroutines to reduce the production cost of the PCB. For example, one routine might remove unneeded vias (each via is a drill hole, and costs money to make). Another might round edges of conductor runs, and widen or move runs apart to maintain safe spacing. Another strategy might adjust large copper areas so that they form nets, or large blank areas may get unconnected "checks" of copper. The nets and checks reduce pollution by extending the life of the etchant batch, and speed production by evening-out the copper concentration in the etching bath.
Some systems provide design rule checking to validate the design for electrical connectivity and clearance, rules for board manufacture, assembly and test, heat flow and other errors.
The silk-screen, solder mask, and solder paste stencil(s) are often designed as auxiliary layers.
Finally, the copper layers are then converted to Gerber files, a format of numerical control file for a photoplotter. Historically, an additional aperture file was required to link each numerically designated aperture referred to in the Gerber file with an actual shape to be plotted. Newer Gerber files embed the aperture information in the Gerber file itself. The hole locations are encoded in drill files (Excellon files). The drill files may be sorted to minimize drill-head movement time, and bit changes.
